Ferroelectric layers are formed in some microelectronic devices, for example in non-volatile memory devices. As wafer diameters increase in the microelectronic industry, it becomes desirable to form the ferroelectric layers on the larger wafers, for example 300 millimeter wafers, to accrue the associated lower fabrication costs. Forming ferroelectric layers with desired qualities such as uniform stoichiometry and orientation on larger substrates has been problematic. Loss of elements such as lead from the layers undesirably degrades stoichiometry uniformity. Stress in the ferroelectric layers produces unacceptable bow in larger wafers compared to smaller wafers.